Non-volatile memory devices have been developed by the semiconductor integrated circuit industry for various applications such as computers and digital communications. Examples of non-volatile memory devices include conventional flash electronically erasable programmable read-only memories (EEPROMs). A conventional EEPROM typically includes a plurality of NAND gates arranged in an array on a semiconductor chip.
A conventional NAND gate typically has a dual gate structure which includes two field oxide regions on a silicon substrate, a thin tunnel oxide layer between the two field oxide regions, a polysilicon floating gate which comprises a first polysilicon (POLY-1) layer on the tunnel oxide layer, an interpolysilicon dielectric stack such as an oxide-nitride-oxide (ONO) stack on the floating gate, and a polysilicon control gate which comprises a second polysilicon (POLY-2) layer on the dielectric stack. This dual gate structure of a conventional NAND flash memory device is known to a person skilled in the art.
FIG. 1 shows a typical circuit diagram of an array of NAND flash memory gates 2a, 2b, 4a, 4b, 6a and 6b as part of a non-volatile memory device on a semiconductor integrated circuit. The NAND gates 2a, 2b, 4a, 4b, 6a and 6b each have a conventional dual gate structure with a POLY-1 floating gate and a POLY-2 control gate. The floating gates of the NAND gates 2a and 2b are connected together in series along a first bit line 2, the floating gates of the NAND gates 4a and 4b are connected together in series along a second bit line 4, and the floating gates of the NAND gates 6a and 6b are connected together in series along a third bit line 6. The control gates of the NAND gates 2a, 4a and 6a are connected along a first word line 7, and in a similar manner, the control gates of the NAND gates 2b, 4b and 6b are connected along a second word line 8.
The word lines 7 and 8 are implemented to program the respective words comprising the respective bits represented by the memory states stored in the NAND gates 2a, 4a, 6a and 2b, 4b, 6b along the word lines 7 and 8, respectively. When a specific word is being programmed, a "program" voltage V.sub.1 on the order of about 20 V is applied to the word line to enable the bits of the word along the word line to be programmed by the respective bit lines. FIG. 1 shows an example in which the word represented by the memory states of the NAND gates 2a, 4a, 6a, . . . on the word line 7 is being supplied with the "program" voltage V.sub.1 signifying that the word along the word line 7 is being programmed.
A word line which is not being programmed is applied a "no program" voltage V.sub.2 on the order of about 10 V representing a "no program" state for the word represented by the memory states of the NAND gates along the word line to boost the channel potential of the inhibited bitlines. FIG. 1 shows an example in which the word represented by the memory states of the NAND gates 2b, 4b and 6b along the word line 8 is being supplied with the "no program" voltage V.sub.2 signifying that the word along the word line 8 is not being programmed. In a conventional NAND non-volatile memory device, the word line voltage V.sub.1 signifying a "programmed" state for a word line is typically on the order of about 20 V, whereas the word line voltage V.sub.2 signifying a "no program" state for the word line is typically on the order of about 10 V.
As shown in FIG. 1, the conventional NAND flash memory device further includes a plurality of select drain gates 2c, 4c and 6c connected along a voltage line 10 and a plurality of select source gates 2d, 4d and 6d connected along another voltage line 12. The select drain gates 2c, 4c and 6c and the select source gates 2d, 4d and 6d each have a single polysilicon gate structure. The voltage line 10, which is connected to the polysilicon gates of the select drain gates 2c, 4c and 6c, is supplied with a DC voltage V.sub.cc which is constantly maintained on the select drain gates 2c, 4c and 6c during the operation of the NAND flash memory device. In a conventional NAND flash memory device, the DC voltage V.sub.cc for the select drain gates 2c, 4c and 6c is typically on the order of about 3.3 V. In a conventional NAND flash memory device, the select source gate voltage line 12, which is connected to the polysilicon gates of the select source gates 2d, 4d and 6d, is connected to ground. The DC select source gate voltage V.sub.ss is therefore 0 V.
To program a particular bit of a word on a particular word line, such as the word line 7 in FIG. 1, the bit lines 2, 4 and 6 are each supplied with either a "program" voltage or a "program-inhibit" voltage such that the NAND gates 2a, 4a and 6a on the respective bit lines 2, 4 and 6 are programmed with memory states each representing either a logic bit "1" or a logic bit "0". In a conventional NAND flash memory device, a NAND gate is not programmed if the bit line to which the NAND gate is connected is supplied with a "no program" bit line voltage V.sub.cc, which is the same as the DC voltage for the select drain gates 2c, 4c and 6c.
FIG. 1 also shows an example of a self-boosting operation of an inhibited bit line. When the voltage V.sub.cc is applied to the bit line 2, which is an inhibited bit line, the NAND gate 2a on the word line 7 maintains a "program-inhibited" or "no program" state. In a conventional NAND flash memory device, an inhibited state typically signifies a logic bit "1", which is the default bit for NAND gates not being programmed.
Furthermore, in the conventional NAND flash memory device as shown in FIG. 1, a "program state" typically represents a logic bit "0". When the bit line 6 is supplied with the DC select drain gate voltage V.sub.cc, the NAND gate 6a on the word line 7 maintains a "no program" state which signifies a logic bit "1". The bits of the binary word stored on the word line 7 along which the NAND gates 2a, 4a, 6a . . . are disposed are thus programmed with logic bits 101 . . . . The applications of the bit line voltages V.sub.cc and V.sub.ss do not affect the NAND gates 2b, 4b and 6b on the word line 8 because it is applied the "no program" word line voltage V.sub.2. Each of the words on the respective word lines and each of the bits on the respective bit lines can thus be programmed with logic bits "1" and "0", depending upon whether the "program" voltage V.sub.1 or the "no program" voltage V.sub.2 is applied to each of the word lines while the select drain gate voltage V.sub.cc or the select source gate voltage V.sub.ss of 0 V is applied to each of the NAND gates along the respective bit lines.
FIG. 2 is a simplified plan view of a typical physical layout of the conventional NAND flash memory device of FIG. 1 implemented as a semiconductor integrated circuit 14. A first polysilicon (POLY-1) layer 16 is formed on an oxide layer 15 which has been provided on a semiconductor substrate (not shown). The POLY-1 layer 16 has a pattern of vertical strips which serve as the bit lines 2, 4 and 6, respectively. The POLY-1 layer 16 also includes a horizontal polysilicon strip which serves as the select drain gate voltage line 10 for supplying the DC drain gate voltage V.sub.cc to the select drain gates 2c, 4c and 6c in FIG. 1. Referring back to FIG. 2, the POLY-1 layer 16 further includes another horizontal polysilicon strip 12 to serve as the select source gate voltage line 12, which is grounded, for maintaining the select source gates 2d, 4d and 6d at 0 V. The select drain gates 2c, 4c, 6c and the select source gates 2d, 4d, 6d are shown in the physical layout of FIG. 2 as rectangular portions 2c, 4c, 6c and 2d, 4d, 6d of the POLY-1 layer 16 along the select drain gate strip 10 and along the select source gate strip 12, respectively.
The POLY-1 layer 16 has a pattern of channel stop openings, also called channel stop implant windows 21 and 23, between the bit lines 2 and 4 and between the bit lines 4 and 6, respectively. Core field oxide regions 20 and 22, which are portions of the oxide layer 15, are exposed through the respective channel stop implant windows 21 and 23. The channel stop implant window 21 has edges 31 and 33 adjacent the select drain gate strip 10 and the select source gate strip 12, respectively. Similarly, the channel stop implant window 23 has edges 34 and 36 adjacent the select drain gate strip 10 and the select source gate strip 12, respectively. The polysilicon gates of the select drain gates 2c, 4c and 6c are connected to the single select drain gate strip 10, and the polysilicon gates of the select source gates 2d, 4d and 6d are connected to the single select source gate strip 12.
A second polysilicon "POLY-2" layer 26 has a pattern of horizontal strips including strips 7 and 8 which serve as the word lines 7 and 8 in FIG. 1, respectively. As shown in FIG. 2, the horizontal POLY-2 layer strips 7 and 8 serving as the respective word lines are provided on top of the POLY-1 layer 16 and the core field oxide regions 20 and 22. The areas in which the horizontal strips 7 and 8 of the POLY-2 layer 26 overlap the vertical strips 2, 4 and 6 of the POLY-1 layer 16 form the respective NAND gates 2a, 4a, 6a, 2b, 4b and 6b. In a conventional NAND flash memory device, an interpolysilicon dielectric stack such as an oxide-nitride-oxide (ONO) trilayer stack (not shown) is provided between the POLY-1 layer 16 and the POLY-2 layer 26 in the areas 2a, 4a, 6a, 2b, 4b and 6b to form the respective NAND gates. The interpolysilicon dielectric stack is conventional and is known to a person skilled in the art. The select drain gates 2c, 4c and 6c and the select source gates 2d, 4d and 6d each have only one polysilicon layer, and therefore no interpolysilicon dielectric stack is provided on these select gates.
The dimensions of NAND flash memory devices have been aggressively shrunk down in recent years in order to provide larger scale integration. When the dimensions of the NAND devices are shrunk down to a very small size, the physical distance between adjacent bit lines becomes short and the channel stop implant window between the adjacent bit lines becomes narrow. A field turn-on in the substrate region under the field oxide region beneath the polysilicon select drain gate strip 10 may be effected by applying the DC select drain gate voltage V.sub.cc to one of the bit lines 2, for example, and grounding another bit line 4, for example, adjacent to the bit line 2 which is applied the voltage V.sub.cc, during the programming of the bits stored in the NAND memory gates 2a and 4a on the respective bit lines 2 and 4. The field turn-on in the substrate region under the select gate transistor field oxide region may cause the bits which are supposed to be program-inhibited with logic bit "1" to be "turned on" to a programmed memory state indicating logic bit "0". Therefore, a field turn-on is undesirable in that it causes a program disturbance during the programming of the NAND memory gates in a conventional non-volatile memory device.
In a conventional NAND non-volatile memory device, as the field regions are shrunk, there could be a leakage path between bit lines which results from a relatively low doping concentration in the substrate region under the select drain gate transistor field oxide region. When a field turn-on occurs, an excess leakage current will flow between the bit lines during the programming of the NAND device, thereby causing program disturbance and product failure. Therefore, there is a need for a NAND flash memory device and a method of programming the memory device to eliminate the program disturbance caused by the field turn-on when some of the bit lines are applied the voltage V.sub.cc while others are grounded.